Method and apparatus for enabling a timing synchronization circuit

ABSTRACT

A timing control circuit includes a synchronization circuit and a detection circuit. The synchronization circuit includes a main delay line configured to receive an input clock signal and delay the input clock signal by a time interval to generate an output clock signal and a control circuit configured to control the main delay line to vary the time interval to synchronize the input clock signal with a feedback clock signal generated from the output clock signal responsive to assertion of an enable signal. The detection circuit is configured to receive the input clock signal and the feedback clock signal, detect a phase alignment error between the input clock signal and the feedback clock signal, and assert the enable signal responsive to the phase alignment error exceeding a predetermined amount. A method for synchronizing clock signals includes receiving an input clock signal; delaying the input clock signal by a time interval to generate an output clock signal; controlling the time interval to synchronize the input clock signal with a feedback clock signal generated from the output clock signal responsive to assertion of an enable signal; detecting a phase alignment error between the input clock signal and the feedback clock signal; and asserting the enable signal responsive to the phase alignment error exceeding a predetermined amount.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates generally to the field of semiconductor devicemanufacturing and, more particularly, to a method and apparatus forenabling a timing synchronization circuit.

2. Description of the Related Art

Many high speed electronic systems possess critical timing requirementsthat dictate a need to generate a periodic clock waveform possessing aprecise timing relationship with respect to some reference signal. Theimproved performance of computing integrated circuits and the growingtrend to include several computing devices on the same board present achallenge with respect to synchronizing the time frames of all thecomponents.

While the operation of all components in the system should be highlysynchronized, i.e., the maximum skew in time between significant edgesof the internally generated clocks of all the components should beminimized, it is not enough to feed the reference clock of the system toall the components. This is because different chips may have differentmanufacturing parameters, which, when taken together with additionalfactors such as ambient temperature, voltage, and processing variations,may lead to large differences in the phases of the respective chipgenerated clocks.

Conventionally, synchronization is achieved by using a timing circuit,such as a digital delay locked loop (DDLL) circuit, a clock synchronizeddelay (CSD) circuit, or a synchronous mirror delay (SMD) circuit todetect the phase difference between clock signals of the same frequencyand produce a digital signal related to the phase difference. A commonresponse in a synchronization circuit to high frequency noise is togenerate a shift in one direction (i.e., to increase or decrease thedelay), followed by a subsequent shift in the opposite direction (i.e.,because the first shift was not representative of an actual phasedifference between the input and output clocks). This undesirableshifting results in jitter in the output clock signal. This jitter inthe output signal may reduce the stability of, or cause an error in, thedigital device relying on the output clock.

DDLL circuits typically require a relatively large number of clockcycles to synchronize. As a result of this significant lock period, DDLLcircuits are not typically disabled after a lock is achieved to conservepower. DDLL circuits are also not well suited to handling largetemperature or voltage shifts due to their slow response time.

CSD and SMD circuits have been developed for providing a fast lockcapability (e.g., within 1-4 clock cycles after initialization). Onedrawback of such circuits is noise sensitivity, which may result inconsiderable jitter due to process, voltage, and temperature (PVT)variations.

The present invention is directed to overcoming, or at least reducingthe effects of, one or more of the problems set forth above.

SUMMARY OF THE INVENTION

One aspect of the present invention is seen in a timing control circuitincluding a synchronization circuit and a detection circuit. Thesynchronization circuit includes a main delay line configured to receivean input clock signal and delay the input clock signal by a timeinterval to generate an output clock signal and a control circuitconfigured to control the main delay line to vary the time interval tosynchronize the input clock signal with the output clock signalresponsive to assertion of an enable signal. The detection circuit isconfigured to receive the input clock signal and a feedback clocksignal, detect a phase alignment error between the input clock signaland the feedback clock signal, and assert the enable signal responsiveto the phase alignment error exceeding a predetermined amount.

Another aspect of the present invention is seen in a method forsynchronizing clock signals. The method includes receiving an inputclock signal; delaying the input clock signal by a time interval togenerate an output clock signal; controlling the time interval tosynchronize the input clock signal with a feedback clock signalgenerated from the output clock signal responsive to assertion of anenable signal; detecting a phase alignment error between the input clocksignal and the feedback clock signal; and asserting the enable signalresponsive to the phase alignment error exceeding a predeterminedamount.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention may be understood by reference to the followingdescription taken in conjunction with the accompanying drawings, inwhich like reference numerals identify like elements, and in which:

FIG. 1 is a simplified block diagram of a digital system having a timingcontrol circuit in accordance with the present invention;

FIG. 2 is simplified block diagram of the timing control circuit of FIG.1;

FIG. 3 is a simplified block diagram of a clock synchronized delay (CSD)circuit suitable for use as a synchronization circuit in the timingcontrol circuit of FIG. 2;

FIG. 4 is a simplified block diagram of a synchronous mirror delay (SMD)circuit suitable for use as a synchronization circuit in the timingcontrol circuit of FIG. 2; and

FIG. 5 is a simplified block diagram of a detection circuit suitable foruse in the timing control circuit of FIG. 2.

While the invention is susceptible to various modifications andalternative forms, specific embodiments thereof have been shown by wayof example in the drawings and are herein described in detail. It shouldbe understood, however, that the description herein of specificembodiments is not intended to limit the invention to the particularforms disclosed, but on the contrary, the intention is to cover allmodifications, equivalents, and alternatives falling within the spiritand scope of the invention as defined by the appended claims.

DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS

Illustrative embodiments of the invention are described below. In theinterest of clarity, not all features of an actual implementation aredescribed in this specification. It will of course be appreciated thatin the development of any such actual embodiment, numerousimplementation-specific decisions must be made to achieve thedevelopers' specific goals, such as compliance with system-related andbusiness-related constraints, which will vary from one implementation toanother. Moreover, it will be appreciated that such a development effortmight be complex and time-consuming, but would nevertheless be a routineundertaking for those of ordinary skill in the art having the benefit ofthis disclosure.

Referring to FIG. 1, a simplified block diagram of a digital system 100is provided. The digital system 100 includes a first digital device 105coupled to a second digital device 110. The first digital device 105provides a reference clock signal (CLKEX) to the second digital device110. The second digital device 110 uses the CLKEX signal to synchronizeits internal clocks using a timing control circuit 115 and generate anoutput clock signal (Clock Out). As an illustrative example, the seconddigital device 110 may be a memory device that synchronizes its outputdata on a data line 120 with the Clock Out signal.

Turning now to FIG. 2, a simplified block diagram of the timing controlcircuit 115 is illustrated. The timing control circuit 115 includes abuffer 200 in which the input clock signal (CLKEX) is received (andproduces an output signal CLKIN). The CLKIN signal is passed to asynchronization circuit 210. As described in greater detail below inreference to FIGS. 3 and 4, the synchronization circuit 210 delays theCLKIN signal to generate a CLKOUT feedback signal that is synchronizedwith the CLKIN signal. The CLKOUT signal is used to control the internalcircuitry of the digital device 110 (see FIG. 1) such that the dataoutput by the digital device 110 is synchronized with the CLKEX signal.

After the synchronization circuit 210 performs its synchronizationfunction, its control circuitry may be disabled to conserve power andreduce susceptibility to noise in the CLKIN signal. A detection circuit220 is provided for monitoring the degree of synchronization between theCLKIN and CLKOUT signals over time to determine whether the controlcircuitry of the synchronization circuit 210 should be re-enabled toresynchronize the signals, as described in greater detail below inreference to FIG. 5. The detection circuit 220 receives the CLKIN signaland a feedback clock signal (FCLK) corresponding to the actual outputclock signal of the device 110 after the clock signal passes through itsinternal circuitry. The FCLK signal is used as a feedback signal foridentifying phase differences between the CLKEX signal and the actualoutput clock signal of the digital device 110.

To generate the FCLK signal, the CLKOUT signal is passed through a delaymodel 230 that uses a variety of logic components to approximate thedelay introduced in the Clock Out signal by the circuitry of the digitaldevice 110 and the delay in the buffer circuit 200. In an alternativeembodiment, the actual output clock signal may be used to generatefeedback information for the detection circuit 220 (i.e., with theadditional input buffer 200 delay).

Turning now to FIGS. 3 and 4, simplified block diagrams of CSD and SMDcircuits suitable for use as the synchronization circuit 210 areprovided, respectively. The construct and operation of CSD and SMDcircuits are well known to those of ordinary skill in the art. Theinvention is not limited to one of these particular embodiments, asother synchronization circuit designs may be used without departing fromthe spirit and scope of the instant invention.

FIG. 3 illustrates a CSD circuit 300 suitable for use as thesynchronization circuit 210. The CLKIN signal from the buffer 200 ispassed to a main delay line 310 and a CSD control circuit 320 forcontrolling the amount of delay imparted by the main delay like 310. TheCLKIN signal is also passed to a delay model 330 similar to that of FIG.2. In one embodiment, the delay models 230, 330 may be implemented inseparate circuitry, while in another embodiment, the delay models 230,330 may be implemented using the same circuitry and multiplexed into theappropriate circuit path as necessary. For example, when the controlcircuitry of the synchronization circuit 210 is enabled, the delay model230, 330 may be used in the circuit of FIGS. 3 and 4, and when thecontrol circuitry of the synchronization circuit 210 is disabled, thedelay models 230, 330 may be used with the detection circuit 220, asshown in FIG. 2.

The delay model 330 is coupled to a measurement delay line 340. Themeasurement delay line 340 includes a plurality of delay elements (e.g.,individual delay stages with a control gate or a shift register and aplurality of control gates coupled to stages of the shift register).Each delay element has an output that is connected to the CSD controlcircuit 320. In one embodiment, the CSD control circuit 320 may be alatch array having a plurality of parallel latches. When the delayedsignal from the measurement delay line 340 has aligned with the CLKINsignal, the appropriate latch in the CSD control circuit 320 istriggered.

Each output terminal of the plurality of latches in the CSD controlcircuit 320 is connected to the main delay line 310. The main delay line310 includes a plurality of serially cascaded delay elements. The CLKINsignal passes through each of the serially cascaded delay elements untilit reaches the selected delay element that is gated by the latch of theCSD control circuit 320. The output of the main delay line 310 is theCLKOUT signal that is passed to the internal circuitry of the digitaldevice 110.

Turning now to FIG. 4, an SMD circuit 400 suitable for implementing thesynchronization circuit 210 is now described. The CLKIN signal is passedto a delay model 410 similar an construct in construction and operationto the delay modal 330 of FIG. 3. The output of the delay model 410 ispassed to a measurement delay line 420. The measurement delay line 420includes a plurality of serially cascaded delay elements, such as ashift register and a plurality of control gates coupled to stages of theshift register. As with the measurement delay line 340 of FIG. 3, eachelement of the measurement delay line 420 is a delay stage with acontrol gate. The SMD circuit 400 includes an SMD control circuit 430configured to receive the output signals from each stage of themeasurement delay line 420. In the illustrated embodiment, the SMDcontrol circuit 430 is a transfer gate array including a plurality oftransfer gates. In other embodiments, other selection logic may be usedin lieu of transfer gates. The CLKIN signal is connected to each of thetransfer gates. When the delayed signal in the measurement delay line420 has been delayed by an amount that will align the first cycle of thedelayed CLKIN signal with a second cycle of CLKIN signal (i.e.,non-delayed), one of the transfer gates in the SMD control circuit 430is activated. The delayed CLKIN signal is transferred through theselected transfer gate to the main delay line 440.

The main delay line 440 includes plurality of serially connected delayelements each of which has an input terminal connected to the outputterminals of the transfer gate array in the SMD control circuit 430. Theone transfer gate that is activated when the first pulse of the delayedCLKIN signal is aligned with the CLKIN signal is connected to the maindelay line 440. The transferred delayed CLKIN signal is transferred anddelayed through the main delay line 440 to generate the CLKOUT signalthat is passed to the internal circuitry of the digital device 110.

Turning now to FIG. 5, the construct construction and operation of anexemplary embodiment of the detection circuit 220 is provided. Thedetection circuit 220 generates an enable signal for enabling thecontrol circuitry (e.g., the CSD control circuit 320 of FIG. 3 or theSMD control circuit 430 of FIG. 4). Electrical power is not actuallyremoved from the control circuits 320, 430, but rather the state of thecontrol circuits 320, 430 is locked, such that the selected latch (i.e.,in the CSD control circuit 320) or the selected transfer gate (i.e., inthe SMD control circuit 430) cannot change. This locking essentiallyfixes the amount of delay imparted by the main delay line 310, 440. Whenthe detection circuit 220 identifies conditions under which the CLKINand CLKOUT signals should be resynchronized, it sends an enable signalto the control circuit 320, 430 to allow a change in state (e.g., in therespective latch or transfer gate).

In the illustrated embodiment, the detection circuit 220 includes asmall difference phase detector 500 for detecting changes in the phasebetween the CLKIN signal and the FCLK signal (i.e., simulated outputclock signal). The small difference phase detector 500 is configured toprovide a binary signal in response to the phase difference exceeding apredetermined threshold (i.e., in either direction). The output of thesmall difference phase detector 500 is received by a noise filter 510configured to reduce the sensitivity of the output of the smalldifference phase detector 500 to noise. The particular constructconstruction of the noise filter 510 depends on the particularimplementation and the type of noise expected.

In one embodiment, the noise filter 510 may be a majority filter forreducing jitter in the output of the small difference phase detector500. For example, high frequency noise in the CLKIN signal may cause anapparent phase shift between the CLKIN and FCLK signals. The transientnature of the noise may result in the small difference phase detector500 detecting a shift in one direction during one clock cycle followedby a shift in the other direction during a subsequent clock cycle. Thenoise filter 510 (i.e., in a majority filter implementation) waits untilthe output of the small difference phase detector 500 remains at aconstant shift signal condition for a predetermined number of clockcycles. In one exemplary embodiment, the noise filter 510 may be ann-stage shift register that delivers the enable signal after nconsecutive shift signals are asserted. An exemplary number of shiftstages is 2.

The detection circuit 220 also includes a large difference phasedetector 520 configured to detect a large phase difference between theCLKIN and FCLK signals. The large difference phase detector 520, havinga larger activation threshold, allows large phase changes that mayresult from temperature or voltage deviations to bypass the noise filter510 and quickly enable the control circuit 320, 430 of thesynchronization circuit 210 to resynchronize the CLKIN and FCLK signals.

In one exemplary embodiment, the small difference phase detector 500 maybe configured to detect phase differences corresponding to at least onedelay stage in the main delay line 310, 440. The large difference phasedetector 520 may be configured to detect phase differences correspondingto three or more delay stages. The noise filter 510 reduces jitter inthe CLKOUT signal by verifying the persistence of small phase errorsprior to enabling the synchronization circuit 210. The large differencephase detector 520 allows errors cause by significant deviations to beidentified and acted upon without the requisite delay imparted by thenoise filter 510.

Using the detection circuit 220 to selectively enable thesynchronization circuit 210 to re-synchronize the output clock of thedevice 110 with respect to the external clock signal (CLKEX), asdescribed above, has numerous advantages. First, a power savings isrealized by disabling some of the circuitry in the synchronizationcircuit. Second, jitter in the output clock signal is reduced, becausethe synchronization circuit remains in a locked state until conditionsexist that indicate the need to resynchronize. The noise filter 510increases the noise tolerance of the timing control circuit 115 to smallperturbations, yet the large difference phase detector 520 allowssignificant perturbations to be addressed quickly by bypassing the noisefilter 510.

The particular embodiments disclosed above are illustrative only, as theinvention may be modified and practiced in different but equivalentmanners apparent to those skilled in the art having the benefit of theteachings herein. Furthermore, no limitations are intended to thedetails of construction or design herein shown, other than as describedin the claims below. It is therefore evident that the particularembodiments disclosed above may be altered or modified and all suchvariations are considered within the scope and spirit of the invention.Accordingly, the protection sought herein is as set forth in the claimsbelow.

What is claimed:
 1. A timing control circuit, comprising: asynchronization circuit, comprising: a main delay line configured toreceive an input clock signal and delay the input clock signal by a timeinterval to generate an output clock signal; a control circuitconfigured to control the main delay line to vary the time interval tosynchronize the input clock signal with a feedback clock signalgenerated from the output clock signal, control of the main delay lineallowed responsive to assertion of an enable signal; and a detectioncircuit configured to receive the input clock signal and the feedbackclock signal, detect a phase alignment error between the input clocksignal and the feedback clock signal, and assert the enable signalresponsive to the phase alignment error exceeding a predeterminedamount, said detection circuit comprising a noise filter for generatingsaid enable signal.
 2. The timing control circuit of claim 1, whereinthe detection circuit includes a first phase detector configured tocompare the input clock signal and the feedback clock signal and assertthe enable signal responsive to the feedback clock signal being out ofphase with respect to the input clock signal.
 3. The timing controlcircuit of claim 1, wherein the detection circuit comprises: a firstphase detector having a first threshold and being configured to comparethe input clock signal and the feedback clock signal and generate ashift signal responsive to the feedback clock signal being out of phasewith respect to the input clock signal an amount greater than the firstthreshold; and the noise filter coupled to the first phase detector andbeing configured to filter the shift signal to generate the enablesignal.
 4. The timing control circuit of claim 3, wherein the noisefilter is comprises an n-stage delay configured to assert the enablesignal responsive to receiving n occurrences of the first shift signal.5. The timing control circuit of claim 4, wherein n is at least two. 6.The timing control circuit of claim 3, wherein the detection circuitfurther comprises: a second phase detector having a second thresholdlarger than the first threshold and being configured to compare theinput clock signal and the feedback clock signal and assert the enablesignal responsive to the feedback clock signal being out of phase withrespect to the input clock signal an amount greater than the secondthreshold.
 7. The timing control circuit of claim 1, further comprisinga first delay model configured to receive the output clock signal andgenerate the feedback clock signal.
 8. The timing control circuit ofclaim 1, wherein the synchronization circuit comprises a clocksynchronized delay circuit.
 9. The timing control circuit of claim 1,wherein the synchronization circuit comprises a synchronous mirror delaycircuit.
 10. The timing control circuit of claim 1, wherein thesynchronization circuit further comprises: a delay model configured toreceive the input clock signal; and a measurement delay line having aplurality of stages and being coupled to the delay model wherein thecontrol circuit is configured to detect a stage of the measurement delayline where the input clock signal as delayed by the delay model and themeasurement delay line is in phase with the input clock signal.
 11. Thetiming control circuit of claim 10, wherein the measurement delay linecomprises a shift register and a plurality of control gates coupled tostages of the shift register.
 12. The timing control circuit of claim11, wherein the main delay line comprises a plurality of seriallycascaded delay elements, each transfer gate of the transfer gate arrayis associated with an associated one of the serially cascaded delayelements, and the an active transfer gate is configured to transfer theinput clock signal as delayed by the delay model and the measurementdelay line to its associated one of the serially cascaded delayelements.
 13. The timing control circuit of claim 10, wherein thecontrol circuit comprises a latch array comprising a plurality oflatches, each latch is coupled to a respective one of the stages of themeasurement delay line, and one of the latches is active responsive tothe input clock signal as delayed by the delay model and the measurementdelay line being in phase with the input clock signal.
 14. The timingcontrol circuit of claim 13, wherein the main delay line comprises aplurality of serially cascaded delay elements, each latch of the controlcircuit is coupled to an associated one of the serially cascaded delayelements, and the an active latch in the latch array enables itsassociated one of the serially cascaded delay elements.
 15. The timingcontrol circuit of claim 10, wherein the control circuit comprises atransfer gate array comprising a plurality of transfer gates, eachtransfer gate is coupled to a respective one of the stages of themeasurement delay line, and one of the transfer gates is activeresponsive to the input clock signal as delayed by the delay model andthe measurement delay line being in phase with the input clock signal.16. The timing control circuit of claim 1, wherein the control circuitis configured to lock a current state of the main delay line responsiveto the enable signal being deasserted.
 17. A timing control circuit,comprising: a synchronization circuit, comprising: a main delay lineconfigured to receive an input clock signal and delay the input clocksignal by a time interval to generate an output clock signal; a firstdelay model configured to receive the output clock signal and generate afeedback clock signal; a control circuit configured to control the maindelay line to vary the tune interval to synchronize the input clocksignal with the feedback clock signal responsive to assertion of anenable signal; and a detection circuit, comprising: a first phasedetector having a first threshold and being configured to compare theinput clock signal and the feedback clock signal and generate a shiftsignal responsive to the feedback clock signal being out of phase withrespect to the input clock signal an amount greater than the firstthreshold; and a noise filter coupled to the first phase detector andbeing configured to filter the shift signal to generate the enablesignal.
 18. The timing control circuit of claim 17, wherein the noisefilter is comprises an n-stage delay configured to assert the enablesignal responsive to receiving n occurrences of the first shift signal.19. The timing control circuit of claim 18, wherein n is at least two.20. The circuit of claim 17, wherein the detection circuit furthercomprises: a second phase detector having a second threshold larger thanthe first threshold and being configured to compare the input clocksignal and the feedback clock signal and assert the enable signalresponsive to the feedback clock signal being out of phase with respectto the input clock signal an amount greater than the second thresh old.21. The timing control circuit of claim 17, wherein the synchronizationcircuit comprises a clock synchronized delay circuit.
 22. The timingcontrol circuit of claim 17, wherein the synchronization circuitcomprises a synchronous mirror delay circuit.
 23. The timing controlcircuit of claim 17, wherein the control circuit is configured to lock acurrent state of the main delay line responsive to the enable signalbeing deasserted.
 24. A digital system, comprising: a first digitaldevice configured to provide an external clock signal; and a seconddigital device configured to receive the external clock signal, thesecond digital device including: an input buffer configured to receivethe external clock signal and generate an input clock signal basedthereon; and a synchronization circuit, comprising: a main delay linecoupled to the input buffer and configured to delay the input clocksignal by a time interval to generate an output clock signal; a controlcircuit configured to control the main delay line to vary the timeinterval to synchronize the input clock signal with a feedback clocksignal generated from the output clock signal, a state of the controlcircuit locked responsive to assertion of an enable signal; and adetection circuit configured to receive the input clock signal and thefeedback clock signal, detect a phase alignment error between the inputclock signal and the feedback clock signal, and assert the enable signalresponsive to the phase alignment error exceeding a predeterminedamount, said detection circuit comprising a noise filter for generatingsaid enable signal.
 25. The system of claim 24, wherein the detectioncircuit includes a first phase detector configured to compare the inputclock signal and the feedback clock signal and assert the enable signalresponsive to the feedback clock signal being out of phase with respectto the input clock signal.
 26. The system of claim 24, wherein thedetection circuit comprises: a first phase detector having a firstthreshold and being configured to compare the input clock signal and thefeedback clock signal and generate a shift signal responsive to thefeedback clock signal being out of phase with respect to the input clocksignal an amount greater than the first threshold; and the noise filtercoupled to the first phase detector and being configured to filter theshift signal to generate the enable signal.
 27. The system of claim 26,wherein the noise filter is comprises an n-stage delay configured toassert the enable signal responsive to receiving n occurrences of thefirst shift signal.
 28. The system of claim 27, wherein n is at leasttwo.
 29. The system of claim 26, wherein the detection circuit furthercomprises: a second phase detector having a second threshold larger thanthe first threshold and being configured to compare the input clocksignal and the feedback clock signal and assert the enable signalresponsive to the feedback clock signal being out of phase with respectto the input clock signal an amount greater than the second threshold.30. The system of claim 24, further comprising a first delay modelconfigured to receive the output clock signal and generate the feedbackclock signal.
 31. The system of claim 24, wherein the synchronizationcircuit comprises a clock synchronized delay circuit.
 32. The system ofclaim 24, wherein the synchronization circuit comprises a synchronousmirror delay circuit.
 33. The system of claim 24, wherein thesynchronization circuit further comprises: a delay model configured toreceive the input clock signal; and a measurement delay line having aplurality of stages and being coupled to the delay model, wherein thecontrol circuit is configured to detect a stage of the measurement delayline where the input clock signal as delayed by the delay model and themeasurement delay line is in phase with the input clock signal.
 34. Thesystem of claim 33, wherein the measurement delay line comprises a shiftregister and a plurality of control gates coupled to stages of the shiftregister.
 35. The system of claim 34, wherein the main delay linecomprises a plurality of serially cascaded delay elements, each transfergate of the transfer gate array is associated with an associated one ofthe serially cascaded delay elements, and the an active transfer gate isconfigured to transfer the input clock signal as delayed by the delaymodel and the measurement delay line to its associated one of theserially cascaded delay elements.
 36. The system of claim 34, whereinthe control circuit is configured to lock a current state of the maindelay line responsive to the enable signal being deasserted.
 37. Thesystem of claim 33, wherein the control circuit comprises a latch arraycomprising a plurality of latches, each latch is coupled to a respectiveone of the stages of the measurement delay line, and one of the latchesis active responsive to the input clock signal as delayed by the delaymodel and the measurement delay line being in phase with the input clocksignal.
 38. The system of claim 37, wherein the main delay linecomprises a plurality of serially cascaded delay elements, each latch ofthe control circuit is coupled to an associated one of the seriallycascaded delay elements, and the an active latch in the latch arrayenables its associated one of the serially cascaded delay elements. 39.The system of claim 33, wherein the control circuit comprises a transfergate array comprising a plurality of transfer gates, each transfer gateis coupled to a respective one of the stages of the measurment delayline, and one of the transfer gates is active responsive to the inputclock signal as delayed by the delay model and the measurement delayline being in phase with the input clock signal.
 40. A method forsynchronizing clock signals, comprising: receiving an input clocksignal; delaying the input clock signal by a time interval to generatean output clock signal; controlling the time interval to synchronize theinput clock signal with a feedback clock signal generated from theoutput clock signal responsive to assertion of an enable signal;detecting a phase alignment error between the input clock signal and thefeedback clock signal; and asserting the enable signal responsive to thephase alignment error exceeding a predetermined amount, asserting saidenable signal comprising using a noise filter to generate said enablesignal.
 41. The method of claim 40, further comprising: comparing theinput clock signal and the feedback clock signal; and asserting theenable signal responsive to the feedback clock signal being out of phasewith respect to the input clock signal.
 42. The method of claim 40,further comprising: comparing the input clock signal and the feedbackclock signal; generating a shift signal responsive to the feedback clocksignal being out of phase with respect to the input clock signal anamount greater than a first threshold; and filtering the shift signal togenerate the enable signal.
 43. The method of claim 42, whereinfiltering the shift signal further comprises asserting the enable signalresponsive to receiving n occurrences of the a first shift signal. 44.The method of claim 43, wherein filtering the shift signal furthercomprises asserting the enable signal responsive to receiving at leasttwo occurrences of the first shift signal.
 45. The method of claim 42,further comprising asserting the enable signal responsive to thefeedback clock signal being out of phase with respect to the input clocksignal an amount greater than a second threshold.
 46. The method ofclaim 40, further comprising delaying the output clock signal togenerate the feedback clock, signal.
 47. The method of claim 40, whereindelaying the input clock signal further comprises delaying the inputclock signal in a delay line, and the method further comprises locking acurrent state of the delay line responsive to the enable signal beingdeasserted.
 48. A method for synchronizing clock signals, comprising:receiving an input clock signal; delaying the input clock signal by atime interval to generate an output clock signal; controlling the timeinterval to synchronize the input clock signal with a feedback clockgenerated from the output clock signal responsive to assertion of anenable signal; detecting a phase alignment error between the input clocksignal and the feedback clock signal; generating a first shift signalresponsive to the phase alignment error exceeding a first predeterminedamount; filtering the first shift signal to generate a filtered shiftsignal; generating a second shift signal responsive to the phasealignment error exceeding a second predetermined amount; and assertingthe enable signal based on either of the filtered shift signal and thesecond shift signal being asserted.
 49. A device, comprising: means forreceiving an input clock signal; means for delaying the input clocksignal by a time interval to generate an output clock signal; means forcontrolling the time interval to synchronize the input clock signal witha feedback clock signal generated from the output clock signalresponsive to assertion of an enable signal; means for detecting a phasealignment error between the input clock signal and the feedback clocksignal; and means for asserting the enable signal responsive to thephase alignment error exceeding a predetermined amount, said means forasserting said enable signal comprising means for using a noise filterto generate said enable signal.
 50. A device, comprising: means forreceiving an input clock signal; means for delaying the input clocksignal by a time interval to generate an output clock signal; means forcontrolling the time interval to synchronize the input clock signal witha feedback clock signal generated from the output clock signalresponsive to assertion of an enable signal; means for detecting a phasealignment error between the input clock signal and the feedback clocksignal; means for generating a first shift signal responsive to thephase alignment error exceeding a first predetermined amount; means forfiltering the first shift signal to generate a filtered shift signal;means for generating a second shift signal responsive to the phasealignment error exceeding a second predetermined amount; and means forasserting the enable signal based on either of this filtered shiftsignal and the second shift signal being asserted.
 51. A timing controlcircuit, comprising: a synchronization circuit to delay an input clocksignal and generate a feedback clock signal that is substantiallysynchronized with the input clock signal, said synchronization circuitcomprising a main delay line configured to delay said input signal and acontrol circuit configured to control the main delay line to synchronizethe input clock signal with a the feedback clock signal; and a detectioncircuit communicatively coupled to the synchronization circuit tomonitor a degree of synchronization between the input clock signal andthe feedback clock signal over time to selectively enableresynchronization of the input clock signal and the feedback signalbased on the degree of synchronization, said detection circuitcomprising a noise filter for generating an enable signal for enablingsaid resynchronization.
 52. The circuit of claim 51, wherein the degreeof synchronization is based on a phase alignment error between the inputclock signal and the feedback clock signal.
 53. The circuit of claim 52,wherein the detection circuit asserts an the enable signal to thesynchronization circuit responsive to the phase alignment errorexceeding a predetermined amount.
 54. The circuit of claim 51, whereinthe detection circuit comprises: a first phase detector having a firstthreshold and being configured to compare the input clock signal and thefeedback clock signal and generate a shift signal responsive to thefeedback clock signal being out of phase with respect to the input clocksignal an amount greater than the first threshold; and the noise filtercomprises a majority filter coupled to the first phase detector andbeing configured to filter the shift signal to generate the enablesignal.
 55. The circuit of claim 54, wherein the detection circuitfurther comprises: a second phase detector having a second thresholdlarger than the first threshold and being configured to compare theinput clock signal and the feedback clock signal and assert the enablesignal responsive to the feedback clock signal being out of phase withrespect to the input clock signal an amount greater than the secondthreshold.
 56. A timing control circuit, comprising: a synchronizationcircuit to delay an input clock signal and generate a feedback clocksignal that is substantially synchronized with the input clock signal,said synchronization circuit comprising a main delay line configured todelay said input clock signal and a control circuit configured tocontrol the main delay line to synchronize the input clock signal with athe feedback clock signal and further configured to have a locked stateresponsive to an enable signal; and a detection circuit to receive theinput clock signal and the feedback clock signal, determine differencebetween the input clock signal and the feedback clock signal and providean the enable signal to the synchronization circuit responsive to thedetermined difference to allow the state of the control circuit to bechanged, said detection circuit comprising a noise filter for generatingsaid enable signal.
 57. The circuit of claim 56, wherein the differencebetween the input clock signal and the feedback clock signal is based ona phase alignment error between the input clock signal and the feedbackclock signal.
 58. The circuit of claim 57, wherein the detection circuitasserts the enable signal responsive to the phase alignment errorexceeding a predetermined amount.
 59. The circuit of claim 56, whereinthe detection circuit comprises: a first phase detector having a firstthreshold and being configured to compare the input clock signal and thefeedback clock signal and generate a shift signal responsive to thefeedback clock signal being out of phase with respect to the input clocksignal an amount greater than the first threshold; and the noise filtercoupled to the first phase detector and being configured to filter theshift signal to generate the enable signal.
 60. The circuit of claim 59,wherein the detection circuit further comprises: a second phase detectorhaving a second threshold larger than the first threshold and beingconfigured to compare the input clock signal and the feedback clocksignal and assert the enable signal responsive to the feedback clocksignal being out of phase with respect to the input clock signal anamount greater than the second threshold.
 61. An apparatus, comprising:a delay line configured to delay an input clock signal by a timeinterval to generate an output clock signal; a control circuit coupledto the delay line and configured to control the time interval tosynchronize the input clock signal with a feedback clock generated fromthe output clock signal responsive to assertion of an enable signal; adetection circuit coupled to the control circuit and configured todetect a phase alignment error between the input clock signal and thefeedback clock signal and generate a first shift signal responsive tothe phase alignment error exceeding a first predetermined amount, thedetection circuit further configured to filter the first shift signal togenerate a filtered shift signal, the detection circuit furtherconfigured to generate a second shift signal responsive to the phasealignment error exceeding a second predetermined amount and assert theenable signal based on either of the filtered shift signal and thesecond shift signal being asserted.
 62. The apparatus of claim 61wherein the detection circuit comprises: a first phase detectorconfigured to compare the input clock signal and the feedback clocksignal and provide the first shift signal responsive to the phasealignment error exceeding the first predetermined amount; and a secondphase detector configured to compare the input clock signal and thefeedback clock signal and provide the second shift signal responsive tothe phase alignment error exceeding the second predetermined amount. 63.The apparatus of claim 62 wherein the first predetermined amount isdifferent than the second predetermined amount.